Model-weight capacity
As parameter counts grow, placing every weight in expensive high-speed memory is not always economical. HBF can provide a much larger near-compute weight tier.
HBF · HIGH BANDWIDTH FLASH
A larger, near-compute capacity tier for AI inference
HBF is not simply a faster SSD, nor is it a one-for-one substitute for HBM. It is an emerging memory tier that aims to combine flash-scale capacity with high parallelism and a much shorter path to compute.
COMPUTESRAM-CIMIn-array compute · hot data
CAPACITYHBFWeights · KV cache · MoE experts
STORAGESSDCheckpoints · datasets · cold data
01 · DEFINITION
What is HBF?
HBF, or High Bandwidth Flash, is an emerging flash architecture for AI inference. It builds on the density and non-volatility of NAND while using highly parallel data paths, advanced packaging and near-compute connectivity to feed much larger model state into the processor efficiently.
SK hynix and Sandisk describe HBF as a new memory tier between HBM and SSD. Its system value is not one peak number: it is the ability to keep model weights, long-context KV cache and MoE experts closer to compute at a more scalable capacity, power and cost point.
Industry reference: SK hynix and Sandisk on HBF standardization ↗
02 · COMPARISON
HBF vs HBM vs SSD
| Dimension | HBM | HBF | SSD |
|---|---|---|---|
| Medium | DRAM | NAND flash | NAND flash |
| Primary goal | Extreme bandwidth and low latency | Capacity with sustained bandwidth | General-purpose high-capacity storage |
| System position | Adjacent to the accelerator | Near-compute capacity tier | PCIe / NVMe storage tier |
| Best-fit data | Hottest tensors and active KV | Weights, experts and warm KV | Checkpoints, datasets and cold data |
| Relationship | The three tiers can work together rather than forcing a single-memory choice. | ||
03 · AI INFERENCE
Why HBF matters for large models
KV cache scaling
Long context and request concurrency continuously expand KV cache. Tiering keeps the most active state in faster memory and moves warmer state into a larger capacity layer.
MoE expert storage
Mixture-of-Experts models activate only part of the network per token but must retain the full expert set. A near-compute capacity tier can reduce expert movement.
Less data movement
Co-designing memory, interconnects, compute and models shortens the path data travels, reducing latency and energy beyond what more arithmetic alone can deliver.
REEXEN · MEMORY–PROCESSOR–MODEL
REEXEN: HBF × SRAM Computing in Memory
REEXEN uses SRAM Computing in Memory (SRAM-CIM) as a compute foundation and explores HBF, TSV, hybrid bonding and system software as one architecture. HBF and a CIM chip are different devices: HBF supplies a large near-compute data tier, while SRAM-CIM executes frequent operations inside the memory array. Together they shorten the path between model state and arithmetic.
- HBF: capacity for model weights, KV cache and intermediate state
- SRAM-CIM: high-frequency in-array compute with less weight movement
- Advanced interconnects: shorter, wider paths between memory and compute
- MPM co-design: Memory, Processor and Model optimized together
04 · FAQ
High Bandwidth Flash FAQ
What is High Bandwidth Flash (HBF)?
High Bandwidth Flash is an emerging NAND flash architecture for AI systems. It combines flash-scale, non-volatile capacity with wider parallel data paths, advanced packaging and a position closer to the processor than a conventional SSD.
How is HBF different from HBM?
HBM is DRAM-based and optimized for extremely high bandwidth and low latency. HBF is NAND-based and emphasizes much larger non-volatile capacity and scalable cost. HBF is generally positioned as a complementary tier between HBM and SSD, not a one-for-one replacement for HBM.
How is HBF different from an NVMe SSD?
An NVMe SSD is a general-purpose block-storage device connected over PCIe. HBF is intended to expose more flash parallelism through a shorter, package-local or near-compute data path designed around AI access patterns. Interfaces and packaging will evolve as the industry standard matures.
Why does AI inference need HBF?
Large-model inference repeatedly reads model weights, grows KV cache with context and concurrency, and may need to hold a complete set of MoE experts. HBF can provide a larger near-compute capacity tier while the hottest data remains in SRAM, HBM or DRAM.
Is HBF the same as a compute-in-memory chip?
No. HBF is a high-capacity flash-memory tier, while a compute-in-memory or CIM chip performs arithmetic inside or next to a memory array. They can work together: HBF holds large model state, and SRAM-CIM processes frequently used data over a shorter path.
How does REEXEN combine HBF and SRAM-CIM?
REEXEN uses SRAM Computing in Memory as a compute foundation and explores HBF, advanced vertical interconnects and system software together. The goal is to place model weights, KV cache and compute units on shorter, more parallel data paths across edge and cloud inference.
CONTACT · HBF TECHNICAL DISCUSSION
Bring us your model, capacity and inference requirements
For a productive first conversation, share model size and precision, context length and concurrency targets, plus your current HBM, DRAM or SSD configuration.